ZYNQ之PS DMA(PL330)的使用

ZYNQ 芯片中有 2 种类型的 DMA:一种是集成在 PS 中的硬核 DMA(PL330),另一种是 PL 中使用的软核 AXI DMA IP。本篇文章先介绍硬核 DMA 的使用方法及注意事项,后续两篇文章介绍 AXI DMA IP 和自定义 DMA IP 的使用。

一、PS DMA(PL330)参考资料

主要参考 Xilinx 和 ARM 的官方文档:

  1. ug585 第 9 章
  2. CoreLink DMA-330 DMA Controller Technical Reference Manual r1p2(最新版)

说明:

1)PS DMA 是 ARM 提供的 IP 核

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) PrimeCell peripheral that is developed, tested, and licensed by Arm.

2)PS DMA 又叫 PL330, 或 DMA-330

最初版本叫 PL330,后续改版都叫 DMA-330。所以,在 ug585 文档中见到这两个名字,其实是同一个 DMA。

3)ARM DMA 技术参考文档名字中 rn pn的含义:

Product revision status The rnpn identifier indicates the revision status of the product described in this book, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product.

二、ZYNQ DMA 的应用

ZYNQ之PS DMA(PL330)的使用

一般来说,ZYNQ DMA 支持 2 种类型的数据传输:

  • Memory to memory
  • Memory to/from PL peripheral

2.1 Memory to memory

此种类型,除了支持 PS 的 On-chip RAM 与 DDR 的数据传输,还支持 memory-mapped region (or memory port location) without a FIFO or need for flow control(page 272 of ug585, v1.14),例如:

  • QSPI in Linear addressing mode
  • NOR flash
  • NAND flash

而 PS 的其他 IO 外设则不具备应用 DMA 的条件(page 267 of ug585, v1.14):

All of the DMA transactions use AXI interfaces to move data between the on-chip memory, DDR memory and slave peripherals in the PL. The slave peripherals in the PL normally connect to the DMAC peripheral request interface to control data flow. The DMAC can conceivable access IOPs in the PS, but this is normally not useful because these paths offer no flow control signals.

另外,官方论坛也有关于 PS 外设访问 PS DMA (ARM’s PL-330)的问题及解答:

文中提到:

Specifically, according to Table 4-6 of the TRM (UG585), the SPI controllers are at 0xE000_6000 and 0xE000_7000 then from table 4-1, ‘Other Bus Masters’ column (which includes the DMAC) can see 0xE000_0000 to 0xE02F_FFFF which includes the SPI peripherals.

但又引入另外一个问题:

Using the PS DMA (ARM’s PL-330) for UART transfers, you will face these 2:

1 – the DMA does not have a event (trigger) from the PS UART.

… that’s kind of a show stopper :-)

2 – If there was a trigger, then the problem is to constantly re-program the DMA (it’s not registers to set-up… it’s a real sequence of instructions to generate) to transfer the data.

In the TX direction, it’s kind of feasible as the number of char to send can be used to do it in one DMA re-programming.

On the RX direction, you’ll see it ends up being the DMA doing 1 char transfer and then interrupting the CPU to report the transfer.

In both TX & RX cases, using interrupts and relying on the 64 char deep FIFO of the UART is easier to deal with and also more efficient.

总之,部分 PS IO 外设并不能方便的访问 PS DMA。

2.2 Memory to/from PL peripheral

此种类型,memory 与 PL 外设的数据传输则需要 peripheral request interfaces 接口(AXI_GP)的参与,具体可参考 page 272~278 of ug585, v1.14。

三、ZYNQ DMA 示例

对应上述两种类型的 DMA 应用示例。

3.1 Memory to/from PL peripheral 应用示例

实现方式:PS 的硬核 DMA,经 AXI Central Interconnect,访问 AXI_GP0 接口,AXI_GP0 接口可挂载 BRAM 或者 PL logic。例如:

ZYNQ 学习之路——DMA PS(PL330)基础

文中详细的描述实现过程,可供参考。

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原创文章,作者:sunev,如若转载,请注明出处:https://www.sunev.cn/embedded/1330.html

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