ug472手册介绍了 Xilinx 7 系列 FPGA 的时钟资源,记录一下学习笔记。

解释上述各种颜色的线:
Q:Any of the four clock-capable input pins can drive the PLL/MMCM in the CMT and the BUFH. The BUFG is shown as present in the region, but can be located physically somewhere else in the clock backbone.
Clock-capable pins can drive BUFGs anywhere in the same top/bottom side of the device. There are four tracks in the CMT backbone to support connectivity between vertical regions.
A:红色的线,从 CC 引脚(clock-capable input pins)引出,共 4 根时钟资源走线,驱动 CMT、BUFH 以及 BUFG。
Q:BUFG and BUFH share 12 routing tracks in the HROW and can drive all clocking points in the region. BUFGs can also drive BUFHs (not shown in Figure 1-4). This allows for individual clock enables (CE) on an otherwise global clock distribution.
A:黑色的线,从 BUFG 和 BUFH 引出,BUFG 和 BUFH 共享 12 根时钟走线资源,驱动区域所有的时钟节点(注:logic 对应两侧黑色的细线)。
Q:A GT quad has ten dedicated tracks to drive the CMT and clock buffers in the clock backbone.
A:黄色的线,从 GT 引出,共有 10 根时钟走线资源,驱动 CMT 和 BUF。
Q:The BUFRs located in the I/O bank have four tracks driving clocking points in the logic, CMT, and BUFG.
A:绿色的线,从 BUFR 引出,共 4 根时钟走线资源,驱动 logic(绿色的细线)、CMT 和 BUFG。
Q:CMTs can, with limitations, drive other CMTs in the adjacent regions using the CMT backbone. Similarly, clock-capable pins can drive, with the same limitations, CMTs in adjacent regions.
A:黑色的细线和红色的细线,用于驱动相邻区域的 CMTs。
Clock sources from one region can drive clock buffer resources in its own region as well as in a horizontally adjacent region.
A:一个区域的时钟资源可以驱动所在区域的时钟 buffer,也可以驱动水平相邻区域的时钟 buffer。
Q:CMTs, clock-capable pins, and serial transceivers can drive clocks into the horizontal adjacent region via the BUFH and also connect to the BUFGs in the same top/bottom side of the device.
A:黑、红、黄线,通过 BUFH,也连接至 BUFG,驱动水平相邻区域。
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